1. Field of the Invention
The present invention relates to a processor used in a micro processor, a digital signal processor, or the like.
2. Description of the Related Art
A conventional micro processor or a conventional digital signal processor performs an operation including one or more steps of processing two pieces of input data, so as to obtain the result of the operation. Hereinafter, a conventional processor is described.
FIG. 9 shows a construction of a conventional processor. The processor includes an arithmetic and logic unit (ALU) 1 for performing arithmetic and logic operations, a register 2, a shifter 3, and a register 4. The ALU 1 performs an addition, a subtraction, or the like for the data of a first input and a second input in accordance with an operation control signal. The register 2 temporarily stores data output from the ALU 1. The shifter 3 shifts the data of the second input. A shift count for the shifter 3 is predetermined and stored in the register 4. In another construction, the shifter 3 and the register 4 may be connected to the first input instead of the second input.
It will be described below how the processor having the above construction works by using a typical operation expressed by Equation (1) as an example. EQU Z=X/4+Y/2 (1)
In Equation (1), X and Y represent data of the two inputs, respectively, and Z represents an output data from the processor. In a first step, X is applied to the second input and 0 is applied to the first input. As a control signal, an adding instruction (ADD) is applied to the ALU 1. In accordance with the value stored in the register 4, the shifter 3 shifts X to the right by 2 bits, so as to obtain X/4, which is stored in the register 2.
In a second step, the value stored in the register 2 which is obtained in the first step, i.e., X/4 is applied to the first input, and Y is applied to the second input. The shifter 3 shifts Y to the right by 1 bit in accordance with the value stored in the register 4. An adding instruction (ADD) is again applied to the ALU 1, so as to obtain Z expressed by Equation (1).
However, the processor has a problem in that, in order to obtain an operation result with a reduced error in the conventional construction, it is necessary to control the shifting by determining which is first performed, the shifting or the operation, depending on the characteristics of the input data (i.e., the value of the input data), and by setting the contents of the register 4 by a program. The problem will be analyzed below in detail.
As to the timing of the shifting, for example, there are three calculating manners for Equation (1). EQU Z=(X+2Y)/4 (2) EQU Z=(X/2+Y)/2 (3) EQU Z=X/4+Y/2 (4)
In the processor shown in FIG. 9, for example, in Equation (2), Y which is shifted to the left by 1 bit is added to X, and then a shifting to the right by 2 bits is performed, so as to obtain Z. In Equation (3), Y which is shifted to the left by 0 bit is added to X which is shifted to the right by 1 bit, and then a shifting to the right by 1 bit is performed, so as to obtain Z. In Equation (4), the calculating manner is the same as that in Equation (1), so that the shifting is performed as described above. In the operations of Equations (2), (3), and (4), the probability that an overflow occurs in the ALU 1 decreases in the order of (2), (3), and (4). However, the round off error in the operation becomes larger in this order. Therefore, in order to obtain an optimum operation result without causing an overflow and with a small error, optimum processing must be performed in view of the shift count to the left by which the overflow will occur in the ALU 1 depending on the value of the input data. For this purpose, it is necessary to determine the timing of the shifting, that is, whether the shifting is performed before the addition of the two pieces of data, or after the addition of the two pieces of data by a program, and to set the contents of the register 4, for each processing. This constitutes the problem.